FIG. 1 shows a prior art phase-locked loop (PLL) 100 as generally comprising a phase detector 105, a charge pump 110, a loop filter 115, and a voltage controlled oscillator (VCO) 120, all coupled in series. PLLs are often used in integrated circuits to internally generate clock signals with reference to an externally provided system clock signal.
In response to a voltage at its input, VCO 120 outputs an oscillating signal CLK that is the output signal of PLL 100. Typically, the frequency of the CLK signal tends to increase as the voltage at the input of VCO 120 increases. The CLK signal is fed back to the phase detector 105, which compares the phase of the CLK signal to the phase of a reference clock signal REFCLK having the desired lock frequency for the PLL 100. Phase detector 105 supplies voltage pulses in response to detecting phase differences between the CLK signal and the REFCLK signal. For example, when the frequency of the CLK signal is less than that of REFCLK, phase detector 105 supplies one or more "up" pulses to raise the voltage at the input of VCO 120. Conversely, when the frequency of the CLK signal is greater than that of REFCLK, phase detector 105 supplies one or more "down" pulses to lower the voltage at the input of VCO 120.
Charge pump 110 responds to voltage pulses by outputting current pulses that loop filter 115, which often includes a large capacitor, averages to define a DC voltage at the input of VCO 120. Charge pump 110 responds to up pulses by outputting "positive" current pulses that add charge to the capacitor of loop filter 115, raising the DC voltage at the input of VCO 120. Charge pump 110 responds to down pulses by outputting "negative" current pulses that remove charge from the capacitor of loop filter 115, lowering the DC voltage at the input of VCO 120. When the frequency of the CLK signal is equal to the frequency of REFCLK, PLL 100 is "in lock," and the DC voltage of loop filter 115 is essentially constant. Thus, when PLL 100 is in lock, loop filter 115 may be modeled as a DC voltage supply such as a battery.
Charge pump 110 is an important component of PLL 100 as charge pump 110 in many ways determines the maximum range of lock frequencies for PLL 100. Further, charge pump 110 may require a significant amount of semiconductor die space to implement and relatively high voltages to operate, thus increasing the overall size and power consumption of PLL 100.
FIG. 2 shows a prior art gate-switched charge pump circuit having a maximum lock frequency of approximately 150 MHz for current processing technology. Gate-switched charge pump circuit 200 includes a p-channel metal oxide semiconductor field effect transistor ("PMOS FET") 205 that acts as a "charging device" by supplying positive current pulses to the gate of FET 205 in response to an UP signal. Gate-switched charge pump circuit 200 also includes an n-channel metal oxide semiconductor ("NMOS") FET 210 that acts as a "discharging device" by supplying negative pulses to the gate of FET 210 in response to a DN signal. FETs 205 and 210 are typically sized such that a single positive current pulse adds as much charge to a capacitive load as a single negative current pulse removes from the capacitive load. Further, the current pulses are typically well-defined such that the amount of charge added or removed by a current pulse is known with some degree of certainty.
To produce well-defined current pulses at the output of a charge pump circuit, the edges of the control signals UP and DN must be sharp. For short current pulses the amount of time normally required to charge the gates of FETs 205 and 210 to switch on FETs 205 and 210 may become significant such that the amount of charge added or removed by current pulses can vary with perturbations in the ramp rate of the input signals. Therefore, for current pulses of relatively short duration, which may occur when the lock frequency of PLL 100 is above 150 MHz, gate-switched charge pump circuits may be undesirable.
FIG. 3 shows a prior art drain-switched charge pump circuit having a higher maximum lock frequency but requiring a relatively large amount of semiconductor die space to implement as well as high operating voltages. Drain-switched charge pump 300 includes charging transistor 305, discharging transistor 310, biasing circuit 315, switches 320-335, and operational amplifier 340. Biasing circuit 315 provides a biasing voltage to the gates of the charging transistor 305 and discharging transistor 310 such that the drain currents of the charging and discharging transistors are equal. Switches 320 and 330 are provided at the drain of charging device 305 to gate positive current pulses in response to signal pair UP and UP#. Similarly, switches 325 and 335 are provided at the drain of discharging device 310 to gate negative current pulses in response to complementary signal pair DN and DN#.
Drain-switched charge pump circuits may be used at higher frequencies than gate-switched charge pump circuits, but drain-switched charge pumps typically require the use of an operational amplifier, such as operational amplifier 340, which is used to maintain nodes 350 and 360 at the same voltage. Operational amplifiers typically require relatively large amounts of die space to implement, and operational amplifiers typically require relatively high value supply voltages. Therefore, the drain-switched charge pump 300 requires more semiconductor die space and increased power consumption when compared to gate-switched charge pumps.